this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev 10 / jul . 00 hyundai semiconductor hy628100b series 128kx8bit cmos sram document title 128k x8 bit 5.0v low power cmos slow sram revision history revision no history draft date remark 10 initial revision history insert jul.14.2000 final
hy628100 b series rev 10 / jul . 00 2 description the hy628100b is a high speed , low power and 1m bit cmos static random access memory organized as 131,072 words by 8bit. the hy628100b uses high performance cmos process technology and designed for high speed low power circuit technology. it is particulary well suited for used in high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup(l/ll-part) - . 2.0v(min) data retention standard pin configuration - . 32 - sop - 525 mil - . 32 - tsopi - 8 x 20 (standard) product voltage speed operation standby current( ua) temperature no (v) ( ns) current / icc ( ma) l ll ( c ) hy628100b 4.5~5.5 50*/ 55/70/85 10 100 20 0~70 comment : 50ns is available with 30pf test load. pin connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs1 i/o8 i/o7 i/o6 i/o5 i/o4 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss cs2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 dq8 dq7 dq6 dq5 dq4 vss dq3 dq2 dq1 a0 a1 a2 a3 a11 a9 a8 a13 /we cs2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 /cs1 sop tsop - i(standard) pin description block diagram pin name pin function /cs1 chip select 1 cs2 chip select 2 /we write enable /oe output enable a0 ~ a16 address input s i/o1 ~ i/o8 data input s / output s vcc power( 4.5v~ 5. 5 v) vss ground memory array 128k x 8 row decoder sense amp write driver data i/o buffer i/o1 i/o8 column decoder add input buffer a0 a16 control logic /cs1 cs2 /oe /we
hy628100 b series rev 10 / jul . 00 2 ordering information part no. speed power temp package hy628100blg 55/70/85 l-part sop hy628100bllg 55/70/85 ll-part sop hy628100blt1 55/70/85 l-part tsopi(standard) hy628100bllt1 55/70/85 ll-part tsopi(standard) comment : 50ns is available with 30pf test load. absolute maximum rating (1) symbol parameter rating unit vcc, v in, v out power supply, input/output voltage -0.5 to 7.0 v t a operating temperature 0 to 70 c t stg storage temperature -65 to 125 c p d power dissipation 1.0 w i out data output current 50 ma t solder lead soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliablity. truth table /cs1 cs2 /we /oe mode i/o power h x x x deselected high-z standby x l x x deselected high-z standby l h h h output disabled high-z active l h h l read data out active l h l x write data in active note : 1. h=v ih , l=v il , x=don't care ( v ih or v il )
hy628100 b series rev 10 / jul . 00 3 recommended dc operating condition t a =0 c to 70 c symbol parameter min. typ. max. unit vcc supply voltage 4.5 5.0 5.5 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0.5 v v il input low voltage -0.5 (1) - 0.8 v note : 1. v il = -1. 5 v for pulse width less than 30ns and not 100% tested dc electrical characteristics vcc = 4.5v~5.5v , t a = 0 c to 70 c , unless otherwise specified symbol parameter test condition min. typ. max. unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs1 = v ih or cs2 = v il or / oe = v ih or /we = v il -1 - 1 ua icc operating power supply current /cs1 = v il , cs2 = v ih, v in = v ih or v il, i i/o = 0ma - - 10 ma i cc1 average operating /cs1 = v il , cs2 = v ih , current v in = v ih or v il cycle time = min, 100% duty, i io = 0ma - - 50 ma i sb ttl standby current (ttl input) /cs1 = v ih or cs2 = v il - - 2 ma i sb1 standby current /cs1 > vcc - 0.2v l - 2 100 ua (cmos input) cs2 < 0.2v or cs2 > vcc - 0.2v ll - 1 20 ua v ol output low voltage i ol = 2.1 ma - - 0.4 v v oh output high voltage i oh = -1ma 2.4 - - v note : typical values are at vcc = 5.0 v, t a = 25 c capacitance temp = 25 c , f= 1.0mhz symbol parameter condition max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf note : these parameters are sampled and not 100% tested
hy628100 b series rev 10 / jul . 00 4 ac characteristics vcc = 4.5v~5.5v , t a = 0 c to 70 c , unless otherwise specified -55 -70 -85 min. max. min. max. min max. 1 t rc read cycle time 55 - 70 - 85 - ns 2 t aa* address access time - 55 - 70 - 85 ns 3 t acs* chip select access time - 55 - 70 - 85 ns 4 t oe output enable to output valid - 25 - 35 - 45 ns 5 t clz chip select to output in low z 10 - 10 - 10 - ns 6 t olz output enable to output in low z 5 - 5 - 5 - ns 7 tchz chip deselection to output in high z 0 20 0 25 0 30 ns 8 tohz out disable to output in high z 0 20 0 25 0 30 ns 9 toh output hold from address change 10 - 10 - 10 - ns 10 twc write cycle time 55 - 70 - 85 - ns 11 tcw chip selection to end of write 45 - 60 - 70 - ns 12 taw address valid to end of write 45 - 60 - 70 - ns 13 tas address set-up time 0 - 0 - 0 - ns 14 twp write pulse width 40 - 50 - 55 - ns 15 twr write recovery time 0 - 0 - 0 - ns 16 twhz write to output in high z 0 20 0 25 0 30 ns 17 tdw data to write time overlap 25 - 30 - 40 - ns 18 tdh data hold from write time 0 - 0 - 0 - ns 19 tow output active from end of write 5 - 5 - 5 - ns comment : taa* and tacs* can meet 50ns with 30pf test load. ac test conditions t a = 0 c to 70 c , unless otherwise specified parameter value input pulse level 0.8v to 2.4v input rise and fall time 5ns input and output timing reference level 1.5v output load cl = 100pf + 1ttl load cl* = 30pf + 1ttl load comment * : test load is 30pf for 50ns ac test loads cl(1) ttl note : including jig and scope capacitance read cycle write cycle symbol parameter # unit
hy628100 b series rev 10 / jul . 00 5 timing diagram read cycle 1(note 1 ,4 ) read cycle 2(note 1,2, 4 ) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2, 4) /cs1 tacs data valid tclz ( 3 ) tchz ( 3 ) data out cs2 notes: 1. read cycle occurs whenever a high on the /we and /oe is low /cs 1 and cs2 are in active status. 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. / c s 1 in high for the standby, low for active c s 2 in low for the standby, high for active data valid high-z addr data out trc / cs1 cs2 / oe taa tacs toe tclz (3) t olz (3) toh t chz (3) tohz (3)
hy628100 b series rev 10 / jul . 00 6 write cycle 1 (1,4,5,9) (/we controlled) write cycle 2 (note 1,4, 5 ,9 ) (/cs1, cs2 controlled) n otes: 1. a write occurs whenever a low on the /we and /oe is low /cs 1 and cs2 are in active state. 2. twr is measured from the earlier of /cs 1 or /we going high or cs2 going low to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the the /cs 1 low transition and cs2 high transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. /oe is continuously low(/oe=v il ) 6. q(data out) is the same phase with the write data of this write cycle. 7. q(data out) is the read data of the next address. 8. transition is measured + 200mv from steady state. this parameter is sampled and not 100% tested. 9. /cs1 in high for the standby, low for active cs2 in low for the standby, high for active data valid addr data out / cs1 cs2 / we twc tcw twr (2) taw twp data in high-z tas twhz (3,8) tdw tdh tow (6) (7) data valid addr data out / cs1 cs2 / we twc tcw twr (2) taw twp data in tdw tdh high-z high-z tas
hy628100 b series rev 10 / jul . 00 7 data retention electric characteristic t a =0 c to 70 c sym parameter test condition min typ max unit v dr vcc for data retention /cs1 > vcc - 0.2v, cs2 < 0.2v or > vcc - 0.2v, vss < v in < vcc 2.0 - - v i ccdr data retention current vcc = 3.0v, /cs1 > vcc - 0.2v l - 2 50 ua cs2 < 0.2v or > vcc - 0.2v, vss < v in < vcc ll - 1 1 0 ua tcdr chip deselect to data retention time 0 - - ns tr operating recovery time trc (2) - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. trc is read cycle time. data retention timing diagram 1 cs1 vdr cs1>vcc-0.2v tcdr tr vss vcc 4.5v 2.2v data retention mode data retention timing diagram 2 0.4v vdr tcdr tr vss vcc 4.5v cs2 data retention mode cs2<0.2v
hy628100 b series rev 10 / jul . 00 8 package information 32pin 525 mil small outline package(g) unit : inch(mm) 0.444(11.278) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.810(20.574) 0.804(20.422) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.102) 0.020(0.508) 0.014(0.356) 0.050(1.27)bsc 0.0125(0.318) 0.0061(0.155) 0.0425(1.080) 0.0235(0.597) 0 deg 8 deg 32pin 8x20mm thin small outline package standard(t1) unit : inch(mm) 0.319(8.103) 0.311(7.900) 0.728(18.491) 0.720(18.288) 0.792(20.117) 0.784(19.914) 0.025(0.64) 0.021(0.54) 0.008(0.21) 0.004(0.10) 0.020(0.50) bsc 0.011(0.27) 0.041(1.05) 0.037(0.95) 0.006(0.15) 0.002(0.05) #1 #32 #16 #17 0.007(0.17)
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